The present invention relates to a clock generator included in a system using a microprocessor for feeding a clock.
A conventional clock generator for the above application includes an output buffer and a PLL (Phase Locked Loop) logic for clock generation. The clock generator is connected to CPUs (Central Processing Units) or similar receivers via a buffer and a damping circuit. The problem with the conventional clock generator is that the driving ability of the output buffer is fixed. As a result, the number of buffers and the number of damping resistors for wave shaping must be matched to the number of loads, scaling up the circuitry outside of the clock generator and thereby lowering the wiring efficiency while increasing the cost.
Technologies relating to the present invention are disclosed in. e.g., Japanese Patent Laid-Open Publication No. 2-187811.